Centurion FFC RAM

This is one of a series of articles about the Centurion FFC board's custom CPU.  In this post we will look at the board's RAM. The board has 4K of RAM but it is accessed in a way that is a little different then a traditional CPU. Instead of the CPU directly addressing the RAM it uses a 12 bit index register to address the RAM before it can be read or written to. For example to write to the RAM the CPU would first write the address to the index register, it can then write data to that location in memory. There is also an option to have the index register automatically increment the address so it doesn't need to be constantly updated when access a range of addresses.

We will start by looking at the circuit for the index registers. These are composed of three 74LS161 synchronous counters. They are split into two separate registers, address bits 0-7 in the low register and 8-11 in the high register. These are loaded by setting the LoadIndexL or LoadIndexH signals, see my last post for how this works. The data being written into these registers come from the Data.Fx bus which in this case is normally from the output of the 2901 chip slice. 

The CEP signal to the counter comes from the MP.H63 microcode bit and will increment the counter when the master clock goes high. This bit can be set in any microcode instruction so it doesn't have to be associated with any RAM activity. 

These two chips allow the CPU to read back the current contents of the index registers. ReadIndexL reads back bits 0-7 and ReadIndexH reads back bits 8-11. The read back allows these registers to behave like an index register on a traditional processor, so when looping through a part of memory the current index doesn't need to be stored anywhere else.

The RAM is composed of two 2K RAM chips which are selected using the A11 line. During a read the ~readRAM signal enables the 74LS240 buffer at the top right to pass the data to the Data bus. During a write the data is latched into the 74LS374 at the bottom and sent to the RAM chips.

The chips in the lower right control the write timing. The 74L121 is a monostable multivibrator. When the ~writeRAM signal goes high it sets the ~Q output low which starts the write cycle. The output will stay low for 100ns which is set by the resistor and capacitor connected to the 74L121. This makes sense since the RAM chips used requires data to be active for 100ns during a write. The next part is a little confusing. The output of the 74LS121 goes to two places. First it goes to the enable input on the 74LS374 which will allow the latched data to pass through to the RAM chips. Second it goes through 4 inverters which will simply add a delay to the signal, and then to the Write Enable signal on the RAM chip. This seems backwards because when the write cycle ends you would want the to RAM go out of write mode before the latch is turned off, but its wired the other way around. It's probably not surprising since these old system tended to have some very tricky timing. 

Here is a look at some micro-code instructions that work with the RAM.

All three instructions work the same way. They enable the constant ROM to get the values that will be written, remember there is one constant byte for each micro-code instruction. The constant passed over the DataIn bus to the 2901 chip slice where the ALU applies the function D + 0 which leaves the value unchanged. The ALU of the 2901 is not impacted by the clock so the immediate value passed right out onto the Data.F bus which goes to the index registers and RAM. The Write value then controls which device the data gets written to.